high voltage rail up to 600v dv/dt immunity +- 50 v/nsec in full tem- perature range driver current capability: 400 ma source, 650 ma sink switching times 50/30 nsec rise/fall with 1nf load cmos/ttl schmitt trigger inputs with hysteresis and pull down under voltage lock out on lower and upper driving section integrated bootstrap diode outputs in phase with inputs description the l6386 is an high-voltage device, manufac- tured with the bcd "off-line" technology. it has a driver structure that enables to drive inde- pendent referenced channel power mos or igbt. the upper (floating) section is enabled to work with voltage rail up to 600v. the logic in- puts are cmos/ttl compatible for ease of inter- facing with controlling devices. july 1999 ? logic uv detection level shifter uv detection r r s v cc lvg driver v cc hin sd hvg driver hvg h.v. to load out lvg pgnd d97in520d lin diag vref + - bootstrap driver vboot cin c boot sgnd 5 7 6 8 9 12 13 14 1 2 3 4 block diagram so14 dip14 ordering numbers: l6386d l6386 l6386 high-voltage high and low side driver 1/10
thermal data symbol parameter so14 dip14 unit r th j-amb thermal resistance junction to ambient 165 100 c/w pin description n. name type function 1 lin i lower driver logic input 2 sd (*) i shut down logic input 3 hin i upper driver logic input 4 vcc i low voltage supply 5 diag o open drain diagnostic output 6 cin i comparator input 7 sgnd ground 8 pgnd power ground 9 lvg (*) o low side driver output 10, 11 n.c. not connected 12 out o upper driver floating driver 13 hvg (*) o high side driver output 14 vboot bootstrapped supply voltage (*) the circuit guarantees 0.3v maximum on the pin (@ isink = 10ma), with vcc >3v. this allows to omit the "bleeder" resistor c onnected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver assures low impe dance also in sd condition. absolute maximum ratings symbol parameter value unit vout output voltage -3 to vboot - 18 v vcc supply voltage - 0.3 to +18 v vboot floating supply voltage -1 to 618 v vhvg upper gate output voltage - 1 to vboot v vlvg lower gate output voltage -0.3 to vcc +0.3 v vi logic input voltage -0.3 to vcc +0.3 v vdiag open drain forced voltage -0.3 to vcc +0.3 v vcin comparator input voltage -0.3 to vcc +0.3 v dvout/dt allowed output slew rate 50 v/ns ptot total power dissipation (tj = 85 c) 750 mw tj junction temperature 150 c ts storage temperature -50 to 150 c note: esd immunity for pins 12, 13 and 14 is guaranteed up to 900v (human body model) lin sd hin v cc diag sgnd cin 1 3 2 4 5 6 7 pgnd n.c. lvg n.c. out hvg v boot 14 13 12 11 10 8 9 d97in521a pin connection l6386 2/10
recommended operating conditions symbol pin parameter test condition min. typ. max. unit vout 12 output voltage note1 580 v vboot- vout 14 floating supply voltage note1 17 v fsw switching frequency hv g,lvg load cl = 1nf 400 khz vcc 4 supply voltage 17 v t j junction temperature -45 125 c note 1: if the condition vboot - vout < 18v is guaranteed, vout can range from -3 to 580v. electrical characteristics ac operation (vcc = 15v; tj = 25c) symbol pin parameter test condition min. typ. max. unit ton 1.3 vs 9, 13 high/low side driver turn-on propagation delay vout = 0v 110 150 ns toff high/low side driver turn-off propagation delay vout = 0v 105 150 ns tsd 2 vs 9,13 shut down to high/low side propagation delay vout = 0v 105 150 ns tr 13,9 rise time cl = 1000pf 50 ns tf 13,9 fall time cl = 1000pf 30 ns dc operation (vcc = 15v; tj = 25c) symbol pin parameter test condition min. typ. max. unit low supply voltage section vcc 4 supply voltage 17 v vccth1 vcc uv turn on threshold 11.5 12 12.5 v vccth2 vcc uv turn off threshold 9.5 10 10.5 v vcchys vcc uv hysteresis 2 v iqccu undervoltage quiescent supply current vcc 11v 200 m a iqcc quiescent current vcc = 15v 250 320 m a bootstrapped supply section vboot 14 bootstrapped supply voltage 17 v vbth1 vboot uv turn on threshold 10.7 11.9 12.9 v vbth2 vboot uv turn off threshold 8.8 9.9 10.7 v vbhys vboot uv hysteresis 2 v iqboot vboot quiescent current vout = vboot 200 m a ilk leakage current vout = vboot = 600v 10 m a rdson bootstrap driver on resistance (*) vcc 3 12.5v; vin = 0v 125 w driving buffers section iso 9, 13 high/low side driver short circuit source current vin = vih (tp < 10 m s) 300 400 ma isi high/low side driver short circuit sink current 500 650 ma logic inputs vil 1,2,3 low level logic threshold voltage 1.5 v vih high level logic threshold voltage 3.6 v iih high level logic input current vin = 15v 50 70 m a iil low level logic input current vin = 0v 1 m a (*) r dson is tested in the following way: r dson = ( v cc - v cboot1 ) - ( v cc - v cboot2 ) i 1 ( v cc, v cboot1 ) - i 2 ( v cc ,v cboot2 ) where i 1 is pin 8 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . l6386 3/10
hin lin sd hout lout v ref v cin diag note: sd active condition is latched until next negative in edge. d97in522a figure 1. timing waveforms dc operation (continued) symbol pin parameter test condition min. typ. max. unit sense comparator vio input offset voltage -10 10 mv iio 6 input bias current vcin 3 0.5 0.2 m a vol 2 open drain low level output voltage, iod = -2.5ma 0.8 v vref comparator reference voltage 0.460 0.5 0.540 v for both high and low side buffers @25?c tamb 0 1 2 3 4 5 c (nf) 0 50 100 150 200 250 time (nsec) tr d99in1054 tf figure 2. typical rise and fall times vs. load capacitance 0246810121416v s (v) 10 10 2 10 3 10 4 iq ( m a) d99in1057 figure 3. quiescent current vs. supply voltage l6386 4/10
bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is normally accom- plished by a high voltage fast recovery diode (fig. 4a). in the l6386 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with in series a diode, as shown in fig. 4b an internal charge pump (fig. 4b) provides the dmos driving voltage . the diode connected in series to the dmos has been added to avoid undesirable turn on of it. cboot selection and charging : to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge : c ext = q gate v gate the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss . it has to be: c boot >>>c ext e.g.: if q gate is 30nc and v gate is 10v, c ext is 3nf. with c boot = 100nf the drop would be 300mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage losses. e.g.: hvg steady state consumption is lower than 200 m a, so if hvg t on is 5ms, c boot has to supply 1 m c to c ext . this charge on a 1 m f ca- pacitor means a voltage drop of 1v. the internal bootstrap driver gives great advan- tages: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 125 ohm). at low frequency this drop can be ne- glected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: v drop = i charge r dson ? v drop = q gate t charge r dson where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1v, if the t charge is 5 m s. in fact: v drop = 30nc 5 m s 125 w ~ 0.8v v drop has to be taken into account when the volt- age drop on c boot is calculated: if this drop is too high, or the circuit topology doesnt allow a sufficient charging time, an external diode can be used. to load d99in1056 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot v boot v s v s v out v boot v out figure 4. bootstrap driver. l6386 5/10
-45 -25 0 25 50 75 100 125 0 50 100 150 200 250 to n ( n s ) t j ( c ) t y p. @ vcc = 15v figure 5. turn on time vs. temperature -45 -25 0 25 50 75 100 125 7 8 9 10 11 12 13 14 15 vbth1 (v) t j ( c ) t y p. @ vcc = 15v figure 8. v boot uv turn on threshold vs. temperature -45 -25 0 25 50 75 100 125 0 50 100 150 200 250 toff (ns) t j ( c ) t y p. @ vcc = 15v figure 6. turn off time vs. temperature -45 -25 0 25 50 75 100 125 7 8 9 10 11 12 13 14 15 vbth2 (v) t j ( c ) t y p. @ vcc = 15v figure 9. v boot uv turn off threshold vs. temperature -45 -25 0 25 50 75 100 125 0 50 100 150 200 250 tsd (ns0 t j ( c ) t y p. @ vcc = 15v figure 7. shutdown time vs. temperature -45 -25 0 25 50 75 100 125 1 1.5 2 2.5 3 vbhys (v) t j ( c ) t y p. @ vcc = 15v figure 10. v boot uv hysteresis l6386 6/10
-45 -25 0 25 50 75 100 125 9 10 11 12 13 14 15 vccth1(v) t j ( c ) t y p. figure 11. vcc uv turn on threshold vs. tem- perature -45 -25 0 25 50 75 100 125 7 8 9 10 11 12 vccth2(v) t j ( c ) t y p. figure 12. vcc uv turn off threshold vs. temperature -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) t j ( c ) t y p. @ vcc = 15v figure 14. output source current vs. tem- perature -45 -25 0 25 50 75 100 125 1 1.5 2 2.5 3 vcchys (v) t j ( c ) t y p. figure 13. vcc uv hysteresis vs. tempera- ture -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) t j ( c ) t y p. @ vcc = 15v figure 15. output sink current vs. tempera- ture l6386 7/10
dip14 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100 outline and mechanical data l6386 8/10
so14 dim. mm inch min.. typ. max.. min.. typ.. max.. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45? (typ.) d (1) 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f (1) 3.8 4 0.150 0.157 g 4.6 5.3 0.181 0.209 l 0.4 1.27 0.016 0.050 m 0.68 0.027 s8? (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). outline and mechanical data (max.) l6386 9/10
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l6386 10/10
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